The present application relates to manufacturing of semiconductor integrated circuits, and more particularly to patterning of semiconductor integrated circuit features using lithography processes. As part of the ongoing world-wide effort to shrink integrated circuit device dimensions, a variety of single-pattern and multiple-pattern lithography processes based on deep ultraviolet (DUV) radiation wavelengths such as 193 nanometers (193 nm) have come into widespread use, although further extension of such arrangements to the patterning of features at production nodes below 10 nm may be problematic. Recent development of extreme ultraviolet (EUV) lithography processes using wavelengths such as 13.5 nm are expected to facilitate the accurate patterning of features at sub-10 nm production nodes, but there remain significant difficulties in the practical implementation of EUV processes. For example, conventional techniques in some cases fail to provide a resist layer that exhibits sufficient etch selectivity relative to an underlying hard mask layer. This can lead to pattern transfer defects such as line breaks due to resist thinning during an etching process. Additionally, elimination of line bridge defects caused by scumming of EUV resist between lines generally requires a resist descum process after lithographic pattern development which further reduces resist thickness available for hard mask etch.